1. Field of the Invention
The present invention relates to a memory device including a semiconductor and a semiconductor device.
2. Description of the Related Art
In recent years, it has been found that electric charge can be retained for a very long period of time by utilizing the very low off-state current of transistors formed using an oxide semiconductor whose band gap is twice or more times that of silicon. For example, the theoretical off-state current (drain current in the off state) of a semiconductor with a band gap of 2.5 eV or more is 10−26 A or less. The band gap of indium-zinc-gallium oxide which is one of oxide semiconductors (see Non Patent Document 1) is 3.2 eV; thus, the theoretical off-state current is 10−31 A or less.
Further, although the off-state current cannot be reduced to the above value, the off-state current of a transistor using an extremely thin film of silicon can be lower than that of a normal transistor by three orders of magnitude (see Patent Document 1).
The use of a memory circuit formed utilizing this as a nonvolatile memory has been proposed (see Patent Documents 1 to 3). FIG. 1 is a circuit diagram of a memory cell in a semiconductor memory device disclosed in each of Patent Documents 1 to 3. The memory cell includes a writing transistor WT, a reading transistor RT, and a storage capacitor SC. Therefore, such a semiconductor memory device is also called a 2Tr1C type semiconductor memory device. A source of the writing transistor WT, a gate of the reading transistor RT, and one electrode of the storage capacitor SC are connected to one another. This portion is called a storage node SN.
Further, a gate of the writing transistor WT is connected to a writing word line WWL, a drain of the writing transistor WT is connected to a bit line BL, a drain of the reading transistor RT is connected to the bit line BL, a source of the reading transistor RT is connected to a source line SL, and the other electrode of the storage capacitor SC is connected to a reading word line RWL.
Since the writing transistor WT formed using an oxide semiconductor has extremely low off-state current, electric charge in the storage capacitor SC can be retained for a sufficient period of time. Further, the electric charge in the storage capacitor SC does not leak at the time of reading, and data is not corrupted at the time of reading.
A normal transistor using silicon is used as the reading transistor RT. Therefore, the absolute value of the threshold voltage of the reading transistor RT is generally lower than 1V. Note that in this specification, when the transistor is an N-channel transistor, the threshold voltage has a positive value, whereas when the transistor is a P-channel transistor, the threshold voltage has a negative value. Accordingly, in this specification, a transistor having a threshold voltage of a positive value is an N-channel transistor, whereas a transistor having a threshold voltage of a negative value is a P-channel transistor.
An operation of the memory cell having such a structure will be described with reference to FIGS. 3A to 3D and FIGS. 4A and 4B. Here, when a potential of the storage capacitor SC is set to 0V or +1 V, data is stored. In order to achieve this, a potential of the bit line BL needs to be 0V or +1 V. Such a potential of the bit line BL is called a data potential. Further, the threshold voltage of the reading transistor WT is set to +1 V, and the threshold voltage of the reading transistor RT is set to +0.5 V.
At the time of data writing, for example, when the potential of the source line SL is set to 0 V, the potential of the bit line BL is set to +1 V, and a potential of the writing word line WWL is set to +2 V, the writing transistor WT is turned on. Further, the potential of the storage node SN is +1 V, and thus the reading transistor RT is also turned on and current flows between the bit line BL and the source line SL, which causes an increase in power consumption (see FIG. 3A).
In order to prevent generation of such a current, the potential of the source line SL is preferably higher than 0V. For example, when the potential of the source line SL is set to +1 V, the current generated in FIG. 3A can be suppressed (see FIG. 3B).
When the potential of the source line SL is set to +1 V and the potential of the bit line BL is +1 V, the potentials of the drain, the source, and the gate of the reading transistor RT are each +1 V, and thus the reading transistor RT is off. Further, when the potential of the bit line BL is 0V, the potentials of the source and the gate are each 0 V, and thus the reading transistor RT is off. As described above, power consumption can be reduced.
When writing is completed, the potential of the writing word line WWL is set to −2 V, and the writing transistor WT is turned off (see FIG. 3C). In order to sufficiently reduce the off-state current of the writing transistor WT, the potential of the gate is preferably lower than one of the potentials of the source and the drain, which is lower than the other, by 0.5 V or more, preferably 1 V or more.
When the potential of the source of the writing transistor WT is higher than or equal to 0 V, the potential of the writing word line WWL may be −1 V. However, as described later, the minimum potential of the source of the writing transistor WT is −1V, and thus the potential of the writing word line WWL needs to be −2 V in order to reduce the off-state current sufficiently.
Next, the potential of the reading word line RWL is reduced from +1 V to 0 V (see FIG. 3D). This is in order to keep the reading transistor RT off. The potential of the storage node SN is −1 V or 0 V. This state is a standby state. During the period in which data is not written to the memory cell or data is not read from the memory cell, the semiconductor memory device is kept in this state, whereby power consumption can be reduced.
At the time of reading data, the potential of the source line SL is set to 0 V, and the bit line BL is charged to +1 V and then put in a floating state (see FIG. 4A). Further, when the potential of the reading word line RWL is set to +1 V, by the capacitive coupling through the storage capacitor SC, the potential of the storage node SN is 0 V or +1 V (see FIG. 4B).
When the potential of the storage node SN is 0 V, the reading transistor RT is off, and thus the potential of the bit line BL remains at +1 V. On the other hand, when the potential of the storage node SN is +1 V, the potential of the bit line BL is 0 V. As described above, by utilizing variation in potential of the bit line BL depending on stored data, data can be read.